1. Field
The present invention relates to a processor and a method for controlling storage-device test unit.
2. Description of the Related Art
Recently, the degree of integration of large scale integration (LSI) circuits has been increasing, and the capacity and the number of random access memories (RAMs) included in LSI circuits have been increasing. Accordingly, the number of test patterns for RAM and the test time of RAM tests have also been increasing.
In LSI circuits, many built-in self-test (BIST) circuits are currently used in testing RAMs included in the LSI circuits.
A BIST circuit includes a pattern generator for generating a test pattern for testing a RAM in an LSI circuit and an address and a control signal for reading/writing the test pattern, and a comparator for comparing the test results. By externally performing the minimum setting of the pattern generator, the BIST circuit automatically tests the RAM and holds the comparison result therein. After the test is completed, the BIST circuit outputs the test result to the outside, and the good or bad of the RAM is checked.
Accordingly, the number of test patterns and the test time can be significantly reduced, compared with a method of reading the details held in the RAM to the outside and comparing the results.
FIG. 17 is a circuit diagram of a known RAM and a known BIST circuit.
An LSI circuit 10 includes a RAM 11 and a BIST circuit 12.
The BIST circuit 12 includes a pattern generator 21, a comparator 25, an address holding circuit 26, a bit position holding circuit 27, and an error flag holding circuit 28.
The pattern generator 21 includes a sequencer 22, a data generator 23, and an address generator 24.
The sequencer 22 generates a predetermined pattern sequence that is a set of a combination of multiple test patterns and an address. The sequencer 22 also outputs a control signal based on the pattern sequence to the RAM 11 and the comparator 25.
The data generator 23 outputs data to be written to the RAM 11 at the time of writing a test pattern or outputs data (expected value) expected to be read from the RAM 11 at the time of reading a test pattern.
The address generator 24 generates an address of data to be written to the RAM 11 or generates an address to be read from the RAM 11, and outputs the address to the RAM 11 and the address holding circuit 26.
The comparator 25 compares the data read from the RAM 11 (read data) with the expected value output from the data generator 23. When the read data does not match the expected value, the comparator 25 outputs a signal that instructs the address holding circuit 26 to hold the address to the address holding circuit 26, outputs the bit position of the mismatch to the bit position holding circuit 27, and outputs an error flag that indicates the occurrence of an error to the error flag holding circuit 28.
The address holding circuit 26 stores the address in the RAM 11 where the error has occurred, on the basis of the instruction from the comparator 25.
The bit position holding circuit 27 stores the bit position output from the comparator 25.
The error flag holding circuit 28 stores the flag indicating whether the RAM 11 has an error.
The good or bad check of the RAM 11 is conducted by reading the error flag from the error flag holding circuit 28 after the test.
The error flag indicates the presence of the defective RAM 11 but does not specify the defective portion. Thus, in addition to the error flag, the address information stored in the address holding circuit 26 and the bit position stored in the bit position holding circuit 27 are used as information for specifying the defective portion.
The RAM 11, the comparator 25, the address holding circuit 26, the bit position holding circuit 27, and the error flag holding circuit 28 constitute a RAM-comparison/result holder 30.
When the LSI circuit 10 includes multiple RAMs (e.g., six RAMs), as illustrated in FIG. 18, multiple RAM-comparison/result holders 30-k (k=1 to 6) are connected to the single pattern generator 21.
Related art includes Japanese Unexamined Patent Application Publication NOs. 2004-86996 and 2006-38782.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-86996    [Patent Document 2] Japanese Laid-Open Patent Publication No. 2006-38782